1. Technical Field
The present invention relates to an image display device, electronic apparatus, portable apparatus, and an image displaying method, and can be applied to e.g. a liquid crystal display based on a multi-bit memory system. According to the present invention, input image data is recorded in a memory part of each pixel, and the grayscale is represented by time-division driving in accordance with the input image data recorded in the memory part. By this feature, in image displaying by a multi-bit memory system, images are displayed with higher efficiency and higher image quality compared with conventional techniques.
2. Background Art
Conventionally, for a liquid crystal display, there has been proposed a so-called area-ratio grayscale system in Japanese Patent Laid-Open No. 2005-1641814 and so on. In this system, one pixel is composed of plural sub-pixels having different areas, and the grayscale of each pixel is varied by changing the area of the region used for displaying through control of the displaying/non-displaying of these plural sub-pixels. Furthermore, this Japanese Patent Laid-Open No. 2005-1641814 proposes a method of providing each one sub-pixel with a one-bit memory and controlling the displaying/non-displaying of the corresponding sub-pixel through recording in this memory to thereby represent the grayscale of input image data composed of multiple bits. Hereinafter, such a system, in which each one pixel is provided with a multi-bit memory and the grayscale of each pixel is represented through recording in this multi-bit memory, will be referred to as a multi-bit memory system.
FIG. 1 is a block diagram showing an image display device of this multi-bit memory system based on the area-ratio grayscale system. In this image display device 1, a display unit 2 is a reflective liquid crystal display panel or a transmissive liquid crystal display panel, and is formed by arranging pixels provided with a color filter of red, green, and blue in a matrix.
FIG. 2 shows the configuration of one pixel 2A in this display unit 2. As shown in FIG. 2, each pixel 2A is composed of plural sub-pixels 2AA to 2AF in which the ratio of the areas of electrodes 3A, 3B, 3C, 3D, 3E, and 3F, which are portions used for displaying, is set to 1:2:4:8:16:32. The respective sub-pixels 2AA to 2AF are formed to have the same configuration, except that the areas of the electrodes 3A to 3F are so designed as to have a certain proportional relationship. In these sub-pixels, liquid crystal cells 5A to 5F including the electrodes 3A to 3F are driven by pixel circuits 4A to 4F, respectively, shown in FIG. 3.
Specifically, the pixel circuits 4A to 4F include a CMOS inverter 6 and a CMOS inverter 7. The CMOS inverter 6 is composed of an N-channel MOS (hereinafter, referred to as NMOS) transistor Q1 and a P-channel MOS (hereinafter, referred to as PMOS) transistor Q2 whose gates and drains are connected to each other. The CMOS inverter 7 is composed of an NMOS transistor Q3 and a PMOS transistor Q4 whose gates and drains are connected to each other similarly. These CMOS inverters 6 and 7 are provided in parallel to each other between a positive power supply line VDD and a negative power supply line VSS, and are connected to each other in a loop manner, so that a memory based on an SRAM (Static Random Access Memory) configuration is formed. In the pixel circuits 4A to 4F, an NMOS transistor Q5 serves as a switch circuit 8 that connects a signal line SIG to these CMOS inverters 6 and 7 and supplies the memory with the logical value of the signal line SIG. Based on this configuration, as shown in FIG. 4, the data through the signal line SIG (FIG. 4(A)) is set in the memory (FIG. 4(C)) through control of the NMOS transistor Q5 by a gate signal GATE (FIG. 4(B)). Symbol V1 denotes the input-side potential of the inverter 6, which is on the input side with respect to this switch circuit 8.
In the pixel circuits 4A to 4F, in accordance with the data thus held in the memory, one of a drive signal FRP (FIG. 4(D)) and a drive signal XFRP (FIG. 4(E)) that are in phase and in antiphase, respectively, with a common voltage VCOM (FIG. 4(G)) applied to the common electrode of the liquid crystal cell 5A (5B to 5F) is selected and applied to the liquid crystal cell 5A (5B to 5F), to thereby drive the liquid crystal cell 5A (5B to 5F). That is, the pixel circuits 4A to 4F control the ON/OFF of a switch circuit 9 composed of an NMOS transistor Q6 and a PMOS transistor Q7 by the output of the inverter 7, to thereby apply the drive signal XFRP, which is in phase with the common potential VCOM, to the liquid crystal cell 5A (5B to 5F) via this switch circuit 9. Furthermore, the pixel circuits 4A to 4F control the ON/OFF of a switch circuit 10 composed of similar NMOS transistor Q8 and PMOS transistor Q9 by the output of the inverter 6, to thereby apply the drive signal FRP, which is in antiphase with the common potential VCOM, to the liquid crystal cell 5A (5B to 5F) via this switch circuit 10. Due to these operations, as shown in FIG. 4, if the potential of the signal line SIG is switched, voltage V5 (FIG. 4(F)) applied to the liquid crystal cell 5A (5B to 5F) is switched from voltage in phase with the common potential VCOM to voltage in antiphase with it at timing t1 of the rising-up of the gate signal GATE subsequent to the switching of the potential of the signal line SIG. This allows the state of the liquid crystal cell 5A (5B to 5F) to be switched between the displaying state and the non-displaying state. The example shown in FIG. 4 corresponds to the case of a so-called normally black mode.
In the image display device 1 (FIG. 1), an interface (IF) 11 inputs, from the configuration of the apparatus provided with this image display device 1, image data SDI as serial data sequentially indicating the grayscales of the respective pixels, a system clock SCK in synchronization with this image data SDI, and a timing signal SCS in synchronization with a vertical synchronizing signal. The interface 11 separates this image data SDI into two-channel data corresponding to odd-numbered lines and even-numbered lines of the display unit 2, and outputs the separated image data DATA to horizontal drivers 12O and 12E. Furthermore, the interface 11 produces a clock LSSCK in synchronization with this image data DATA and outputs it to a timing generator 14. In addition, based on the timing signal SCS, the interface 11 outputs to the timing generator 14 a reset signal RST whose signal level rises up at the timing in synchronization with the vertical synchronizing signal.
The timing generator 14 produces various kinds of timing signals necessary for the operation of the horizontal drivers 12O and 12E and a vertical driver 15 from the clock LSSCK and the reset signal RST, and outputs the produced signals.
The horizontal drivers 12O and 12E operate in accordance with the timing signals output from the timing generator 14, and set the logical level of the signal line SIG in matching with the image data DATA output from the interface 11, for the pixels on the odd-numbered lines and even-numbered lines of the display unit 2.
Specifically, as shown in FIG. 5, in the horizontal drivers 12O and 12E, a timing signal HST that rises up at the timing of the start of a horizontal scanning period is transferred by shift registers (SR) 21A, 21B, . . . sequentially in the line direction, and the image data DATA is latched by sampling latches (SL) 22A, 22B, . . . in accordance with the timing signal output from the respective shift registers 21A, 21B, . . . . This allows the horizontal drivers 12O and 12E to distribute the image data DATA toward the corresponding signal line SIG.
Second latches 23A, 23B, . . . latch and output the latch results by the sampling latches 22A, 22B, . . . . This can output the image data distributed toward the respective signal lines SIG at the same timing. Parallel-serial conversion circuits (PS) 24A, 24B, . . . sequentially select and output the logical values of the respective bits in latch results Lout by the second latches 23A, 23B, . . . in accordance with selection signals SERI, to thereby convert the input image data distributed toward the respective signal lines SIG into serial data and output it.
Specifically, as shown in FIGS. 6 and 7, in the parallel-serial conversion circuits 24A, 24B, . . . , AND circuits 25 to 30 gate logical values Lout0 to Lout5 of the respective bits in the latch result Lout based on the selection signals SERI0 to SERI5 (FIGS. 7(A0) to 7(A5)) whose signal levels rise up sequentially and cyclically. An OR circuit 31 produces the OR signal of the output signals from these AND circuits 25 to 30. The parallel-serial conversion circuits 24A, 24B, . . . output the output signal from this OR circuit 31 via a buffer circuit 32, to thereby output the image data distributed toward the respective signal lines SIG to the signal line SIG as one-bit serial data (FIG. 7(B)).
In matching with the driving of the signal lines SIG by these horizontal drivers 12O and 12E, the vertical driver 15 (FIG. 1) selects the pixels 2A in the display unit 2 on a line-by-line basis in accordance with the timing signal produced by the timing generator 14. Furthermore, for each line, the vertical driver 15 outputs the gate signals GATE0 to GATE5 for sequentially selecting the sub-pixels.
Specifically, as shown in FIG. 8, in the vertical driver 15, a timing signal VST (FIG. 7(C)) whose signal level rises up in synchronization with the vertical synchronizing signal is transferred by shift registers (SR) 41A, 41B, . . . in the vertical direction. In the vertical driver 15, AND circuits 42A0 to 42A5, 42B0 to 42B5, . . . gate selection signals ENB0 to ENB5 (FIGS. 7(D0) to 7(D5)) whose signal levels rise up sequentially and cyclically based on the output signal from the shift registers 41A, 41B, . . . , to thereby produce the gate signals GATE0 to GATE5 (FIGS. 7(E0) to 7(E5)) for sequentially selecting each of the sub-pixels on the respective lines. The vertical driver 15 outputs the gate signals GATE0 to GATE5 to the display unit 2 via buffer circuits 43A0 to 43A5, 43B0 to 43B5, . . . .
Based on the above-described configuration, in the image display device 1 of the example shown in FIG. 1, one signal line is allocated to plural pixels arranged along the vertical direction based on time division, and one signal line SIG is allocated to the sub-pixels in one pixel based on time division. A desired image is displayed through control of the displaying/non-displaying of the respective sub-pixels. The image display device based on such a multi-bit memory system can be widely applied even to the case in which a liquid crystal cell employing both a reflective electrode and a transmissive electrode instead of a reflective liquid crystal or transmissive liquid crystal is used.
However, this multi-bit memory system involves the need to insulate the electrodes of the plural sub-pixels in one pixel from each other. This yields the useless region that does not contribute to displaying in one pixel, which results in a drawback of the lowering of the transmittance and reflectivity of one pixel. This causes a problem of failure in image displaying with high efficiency.
Furthermore, because the grayscale is represented through control of the ON/OFF of the sub-pixels having different areas, the position of the centroid of the region relating to displaying varies from pixel to pixel depending on the luminance of the pixel. This yields a drawback that a fixed pattern dependent upon the arrangement of the sub-pixels is visually recognized at specific grayscales. In addition, there is a drawback that the resolution and the number of grayscales are limited by the processing accuracy of the sub-pixel having the smallest area. Moreover, there is also a drawback that a large number of semiconductor elements need to be provided in one pixel and thus the resolution and the number of grayscales are limited. For these reasons, the above-described system involves a problem that the image quality is insufficient in practical use.